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2.2. Embedded DeviceNet master specification

2.2. Embedded DeviceNet master specification​

 

The Hi5a Embedded DeviceNet master specification is shown in Table 2-2.

 

Table 2‑2 Embedded DeviceNet master specification

IO Connection

POLL

Node address (MAC ID)

0 (Fixed)

Input

FN[1~63].X[1~128]

Output

FN[1~63].Y[1~128]